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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
5.20.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 5-55. Timing Requirements for GPIO Inputs (1) (see Figure 5-44 )
CV DD = 1.05 V
NO.
CV DD = 1.3 V
MIN
MAX
UNIT
1
t w(ACTIVE)
Pulse duration, GPIO input/external interrupt pulse active
2C (1) (2)
ns
2
t w(INACTIVE)
Pulse duration, GPIO input/external interrupt pulse inactive
C
(1) (2)
ns
(1)
(2)
The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to
have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration
must be extended to allow the device enough time to access the GPIO register through the internal bus.
C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
Table 5-56. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-44 )
CV DD = 1.05 V
NO.
PARAMETER
CV DD = 1.3 V
MIN
MAX
UNIT
3
4
t w(GPOH)
t w(GPOL)
Pulse duration, GP[x] output high
Pulse duration, GP[x] output low
3C (1) (2)
3C (1) (2)
ns
ns
(1)
(2)
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
2
GP[x] Input
1
(With IOINTEDGy = 0)
2
GP[x] Input
1
(With IOINTEDGy = 1)
4
3
GP[x] Output
Figure 5-44. GPIO Port Timing
Copyright ? 2010–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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